Impact of Technology on CNTFET-Based Circuits Performance

被引：12
|
作者：
Marani, R. [1 ]
Perri, A. G. [2 ]
机构：
[1] Natl Res Council Italy CNR, Inst Intelligent Ind Technol & Syst Adv Mfg STIIM, I-70125 Bari, Italy
[2] Polytech Univ Bari, Dept Elect & Informat Engn, Elect Devices Lab, I-70125 Bari, Italy
来源：
ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY | 2020年 / 9卷 / 05期
关键词：
Electron Devices; Microelectronics; Theory and Modelling; CARBON NANOTUBE FETS; VIRTUAL-SOURCE MODEL; LOGIC GATES; VERILOG-A; IMPROVE ANALYSIS; COMPACT; DESIGN; TEMPERATURE; SIMULATION; ANALOG;
D O I：
10.1149/2162-8777/ab9185
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
In this paper we present a study of the impact of technology on the CNTFET-based circuits performance. In particular we show the layout of a NOT gate, used as block to build a chain of NOT and a ring oscillator. Then we present the time domain simulations of these circuits in order to see how the parasitic elements could limit the high-speed performances of CNTFETs. (C) 2020 The Electrochemical Society ("ECS"). Published on behalf of ECS by IOP Publishing Limited.
引用
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页数：6
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