Breakdown Voltage Walk-in Phenomenon and Optimization for the Trench-Gate p-Type VDMOS Under Single Avalanche Stress

被引：4
|
作者：
Tong, Xin [1 ]
Liu, Qian [1 ]
Lu, Li [1 ]
Liu, Siyang [1 ]
Wei, Jiaxing [1 ]
Sun, Weifeng [1 ]
Wu, Jianhui [1 ]
Wang, Genyi [2 ]
Yang, Zhuo [2 ]
Zhu, Yuanzheng [2 ]
机构：
[1] Southeast Univ, Natl ASIC Syst Engn Res Ctr, Nanjing 210096, Peoples R China
[2] WUXI NCE Power Co Ltd, Wuxi 214028, Jiangsu, Peoples R China
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2020年 / 67卷 / 06期
基金：
中国国家自然科学基金; 中国博士后科学基金;
关键词：
Avalanche stress; breakdown voltage (BV) walk-in; p-type vertical double-diffused metal-oxide-semiconductor (VDMOS); unclamped inductive switching (UIS); CARRIER DEGRADATION MODES; LDMOS; PLASMA; MOSFET; TRAPS;
D O I：
10.1109/TED.2020.2988860
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An anomalous breakdown voltage (BV) walk-in phenomenon of the trench-gate p-type vertical double-diffused metal-oxide-semiconductor (VDMOS) after single avalanche stress has been experimentally investigated. It is found that the BV of the VDMOS is decreased after the single avalanche stress, while other electrical parameters remain unchanged. T-CAD simulations and emission microscope (EMMI) analysis have been carried out. As a result, the shift of the breakdown point of the VDMOS, which results in the hot hole injection and trapping at the termination region, should be responsible for the BV degradation. A novel device structure with different trench depths in the termination region for the trench-gate p-type VDMOS is proposed to suppress the BV walk-in phenomenon.
引用
收藏
页码：2445 / 2450
页数：6
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