A Distributed Model for Border Traps in Al2O3 - InGaAs MOS Devices

被引：163

作者：

Yuan, Yu ^{[1
]}

Wang, Lingquan ^{[1
]}

Yu, Bo ^{[1
]}

Shin, Byungha ^{[2
]}

Ahn, Jaesoo ^{[2
]}

McIntyre, Paul C.

Asbeck, Peter M. ^{[1
,2
]}

Rodwell, Mark J. W.

Taur, Yuan ^{[1
]}

机构：

[1] Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92093 USA

[2] Stanford Univ, Dept Mat Sci & Engn, Stanford, CA 94305 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2011年 / 32卷 / 04期

关键词：

Border trap; MOS; tunneling; III-V;

D O I：

10.1109/LED.2011.2105241

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A distributed border trap model based on tunneling between the semiconductor surface and trap states in the gate dielectric film is formulated to account for the observed frequency dispersion in the capacitance and conductance of Al2O3/InGaAs MOS devices biased in accumulation. The distributed circuit model is more physical and descriptive than previous lumped circuit border trap models in the literature. The distributed model correctly depicts the frequency dependence of both capacitance and conductance data in accumulation. A border trap volume density is extracted from the quantitative agreement with measured data.

引用

页码：485 / 487

页数：3

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