Early power-aware design & validation: Myth or reality?

Design for low power is crucial for developing and optimizing complex SoCs. Typically, power issues are tackled at the gate-level and backend stages, disconnected from micro-architectural power features or RTL. However, there is growing debate about which stage of the design process is best for dealing with power issues. Leaders associated with the EDA industry and R&D realm will debate whether early power-aware design and validation is viable, and will hold a spirited discussion to determine at which stage of the design process power issues should be tackled: gate level and below, or system level. They will cover various issues involved in automating or establishing a well understood flow/process that delivers quality results, and also will consider organizational hurdles. Attendees will leave this session armed with key questions and valuable insights, and will be challenged to consider if they should change their approach to low-power design. Do the benefits of moving up a level of abstraction - to the architectural level - outweigh the risks of optimizing at lower levels of design? Is such a move truly a viable choice, or merely a myth? Which level of abstraction makes the most sense for power optimization at your company - both now and in the future? Would it be sufficient to tackle power at only one level, disconnected from other levels? Can EDA provide realizable solutions for low-power design that require intimate knowledge of design style and methodology? Panelists will discuss these and other issues to illuminate some of the steps toward a standard ESL design and verification methodology.