Temperature- and Bus Traffic-aware Data Placement in 3D-Stacked Cache

被引：0

作者：

Lee, Seunghan ^{[1
]}

Kang, Kyungsu ^{[1
]}

Kyung, Chong-Min ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Div Elect Engn, Dept Elect Engn & Comp Sci, Taejon, South Korea

来源：

PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP | 2010年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As technology scales, increasing capacity of cache memory leads to increase in leakage power dissipation, especially in three-dimensional (3D) IC with high thermal density. In this paper, we explore how cache data can be mapped on a multi-processor architecture in 3D IC to minimize energy consumption with considering temperature distribution and bus traffic congestion. Simulation results based on ILP (Integer Linear Programming) formulation show that the proposed cache data mapping approach achieves up to 30.7% energy reduction compared to the case of considering temperature distribution only.

引用

页码：352 / 357

页数：6

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