High-Speed and Low-Leakage FinFET SRAM Cell with Enhanced Read and Write Voltage Margins

A new single-ended read asymmetrical SRAM cell with underlap engineered symmetrical FinFETs is proposed in this paper for achieving stronger data stability, enhanced write ability, and suppressed leakage power consumption as compared to previously published six-FinFET memory circuits. With the new SRAM cell, the read data stability, read speed, write voltage margin, and write speed are enhanced by up to 2.7x, 57.6%, 25.5%, and 20.1% while the leakage power consumption is reduced by up to 69.8% without degrading the memory integration density as compared to the previously published six-FinFET SRAM cells in a 15nm FinFET technology.