A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

被引:0
|
作者
Vieira, Joao [1 ]
Giacomin, Edouard [1 ]
Qureshi, Yasir [2 ]
Zapater, Marina [2 ]
Tang, Xifan [1 ]
Kvatinsky, Shahar [3 ]
Atienza, David [2 ]
Gaillardon, Pierre-Emmanuel [1 ]
机构
[1] Univ Utah, LNIS, Salt Lake City, UT 84112 USA
[2] Swiss Fed Inst Technol Lausanne EPFL, ESL, Lausanne, Switzerland
[3] Technion Israel Inst Technol, Andrew & Erna Viterbi Fac Elect Engn, Haifa, Israel
来源
2019 IFIP/IEEE 27TH INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC) | 2019年
基金
欧盟地平线“2020”; 欧洲研究理事会;
关键词
Machine Learning; Edge Devices; Binary Neural Networks; RRAM-based Binary Dot Product Engine; INTERNET; THINGS;
D O I
10.1109/vlsi-soc.2019.8920343
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The need for running complex Machine Learning (ML) algorithms, such as Convolutional Neural Networks (CNNs), in edge devices, which are highly constrained in terms of computing power and energy, makes it important to execute such applications efficiently. The situation has led to the popularization of Binary Neural Networks (BNNs), which significantly reduce execution time and memory requirements by representing the weights (and possibly the data being operated) using only one bit. Because approximately 90% of the operations executed by CNNs and BNNs are convolutions, a significant part of the memory transfers consists of fetching the convolutional kernels. Such kernels are usually small (e.g., 3x3 operands), and particularly in BNNs redundancy is expected. Therefore, equal kernels can be mapped to the same memory addresses, requiring significantly less memory to store them. In this context, this paper presents a custom Binary Dot Product Engine (BDPE) for BNNs that exploits the features of Resistive Random-Access Memories (RRAMs). This new engine allows accelerating the execution of the inference phase of BNNs. The novel BDPE locally stores the most used binary weights and performs binary convolution using computing capabilities enabled by the RRAMs. The system-level gem5 architectural simulator was used together with a C-based ML framework to evaluate the system's performance and obtain power results. Results show that this novel BDPE improves performance by 11.3%, energy efficiency by 7.4% and reduces the number of memory accesses by 10.7% at a cost of less than 0.3% additional die area, when integrated with a 28nm Fully Depleted Silicon On Insulator ARMv8 in-order core, in comparison to a fully-optimized baseline of YoloV3 XNOR-Net running in a unmodified Central Processing Unit.
引用
收藏
页码:160 / 165
页数:6
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