A comparison between noise-immunity design techniques for dynamic logic gates

被引：0

作者：

Gonzalez-Diaz, O. ^{[1
]}

Linares-Aranda, M. ^{[1
]}

Mendoza-Herndndez, F. ^{[2
]}

机构：

[1] INAOE, Puebla, Mexico

[2] Univ Sonora, Phy Res Dept, Hermosillo 83000, Sonora, Mexico

来源：

IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, | 2006年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this work, we analyze three design techniques to enhance the noise immunity of dynamic logic gates. A comparison in Power Consumption, Average Noise Threshold Energy (ANTE) and ANTE-normalized energy (EANTE) between the three techniques is presented. The dynamic logic gates using noise immunity techniques were designed with 0.35 mu m, 0.18 mu m, and 0.09 mu m CMOS process technologies and power supply of 3.3V, 1.8 V, and 1.0 V respectively. The obtained results show that for all technologies used in the simulations the Transparency Window technique [1] presents the best trade-off among noise immunity and performance as technology scales.

引用

页码：484 / +

页数：2

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