Design of an ultralow power CNTFET based 9T SRAM with shared BL and half select free techniques

In this paper, we propose a new design of high-performance ultralow power carbon nanotube field effect transistor (CNTFET)-based nine-transistor static random access memory (SRAM) cell and its implementation using shared bitline (BL) and half-select free techniques. Simulations of the 9T SRAM design, using CNTFET compact model, have presented merits over the silicon-complementary-metal oxide semiconductor (CMOS) SRAM cell in terms of leakage current, power consumption, and stability. Uses of the half-select free technique eliminate the conflict between read and write operations and shared BL technique offers reduced physical layout area and enhanced data access speed. Further, uses of the increased number of tubes or say CNT array in the CNTFET device increases the probability of functionality (>95%) with a high yield SRAM cell.