Reliability of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Re-Distributed Layers

被引：10

作者：

Lau, John ^{[1
]}

Li, Ming ^{[1
]}

Lei, Yang ^{[1
]}

Li, Margie ^{[1
]}

Yong, Qing Xiang ^{[2
]}

Cheng, Zhong ^{[2
]}

Chen, Tony ^{[3
]}

Xu, Iris ^{[3
]}

Fan, Nelson ^{[1
]}

Kuah, Eric ^{[1
]}

Li, Zhang ^{[3
]}

Tan, Kim Hwee ^{[3
]}

Cheung, Y. M. ^{[1
]}

Ng, Eric ^{[1
]}

Lo, Penny ^{[1
]}

Kai, Wu ^{[1
]}

Hao, Ji ^{[1
]}

Beica, Rozalia ^{[4
]}

Wee, Koh Sau

Ran, Jiang

Xi, Cao

Lim, Sze Pei ^{[5
]}

Lee, N. C.

Ko, Cheng-Ta ^{[6
]}

Yang, Henry ^{[6
]}

Chen, Y. H. ^{[6
]}

Tao, Mian ^{[7
]}

Lo, Jeffery ^{[7
]}

Lee, Ricky ^{[7
]}

机构：

[1] ASM Pacific Technol Ltd, Singapore, Singapore

[2] Huawei Technol Co Ltd, Shenzhen, Peoples R China

[3] Jiangyin Changdian Adv Packaging Co Ltd, Wuxi, Jiangsu, Peoples R China

[4] Dow Chem Co USA, Midland, MI 48674 USA

[5] Indium Corp, Chennai, Tamil Nadu, India

[6] Unimicron Technol Corp, Taoyuan, Taiwan

[7] Hong Kong Univ Sci & Technol, Hong Kong, Peoples R China

来源：

2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018) | 2018年

关键词：

D O I：

10.1109/ECTC.2018.00239

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this study, the reliability (thermal-cycling and shock) performances of chip-first and die face-up FOWLP (fan-out wafer-level packaging) with a very large silicon chip (10mmx10mm) embedded in an epoxy molding compound (EMC) package (13.42mmx13.42mm) with three RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level package is assembled on a printed circuit board (PCB) with 908 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level package solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are constructed and analyzed for the fan-out package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the FOWLP solder joints and RDLs under thermal and shock conditions are provided.

引用

页码：1574 / 1582

页数：9

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