Design Considerations for 50G+Backplane Links

被引：0

作者：

Toifl, Thomas ^{[1
]}

Brandli, Matthias ^{[1
]}

Cevrero, Alessandro ^{[1
]}

Francese, Pier Andrea ^{[1
]}

Kossel, Marcel ^{[1
]}

Kull, Lukas ^{[1
]}

Luu, Danny ^{[1
]}

Menolfi, Christian ^{[1
]}

Morf, Thomas ^{[1
]}

Ozkaya, Ilter ^{[1
]}

Yueksel, Hazar ^{[1
]}

机构：

[1] IBM Res, Zurich Res Lab, CH-8003 Ruschlikon, Switzerland

来源：

ESSCIRC CONFERENCE 2016 | 2016年

关键词：

wireline; IO link; backplane; equalization; CTLE; feed-forward equalizer; FFE; decision-feedback equalizer; DFE; MLSE; ADC; 56G; Ethernet; TCM; THP; PAM-4; EQUALIZER; SPEED;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The constantly increasing need for I/O bandwidth push electrical backplane links to data rates of 50Gb/s and above. Although board materials have improved significantly, backplane links are increasingly limited by signal attenuation while suffering from ISI, jitter, device noise and cross-talk. In this paper we summarize these limitations, and show possible directions to cope with them in order to further extend the achievable data rate.

引用

页码：477 / 482

页数：6

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