Automated hardware design using genetic programming, VHDL, and FPGAs

被引：0

作者：

Popp, RL ^{[1
]}

Montana, DJ ^{[1
]}

Gassner, RR ^{[1
]}

Vidaver, G ^{[1
]}

Iyer, S ^{[1
]}

机构：

[1] ALPHATECH Inc, Burlington, MA 01803 USA

来源：

1998 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS, VOLS 1-5 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this research we developed a completely automated approach to hardware design based on integrating three core technologies into one comprehensive system, namely, genetic programming (GP), VHSIC hardware description language (VHDL), and field programmable gate arrays (FPGAs). Our system uses an automated GP engine, as opposed to a human designer, to evolve a hardware design composed of one or more FPGAs that will maximally achieve an application's software requirements. Several variants of our system exist at this point in time. Other variants are currently under development. The focus of this paper is to describe our original system design and its most recent revision to date.

引用

页码：2184 / 2189

页数：6

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