Low-power approaches to high-speed current-steering digital-to-analog converters in 0.18-μm CMOS

This paper will discuss a number of circuit approaches which lower the power consumed by a current steering digital-to-analog converter while maintaining both DC and AC performance levels. An example design provides 14-bit resolution and 200 MSPS conversion rate in a one-poly four-metal (1P4M) 0.18-mu m CMOS process. The inclusion of optional 3.3-V compatible devices allows operation over a supply range from 1.7 to 3.6 V. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8-V operation and as low as 0.28 mW/MSPS at 3.3 V. A measured single-tone SFDR of 70 dB is achieved at a 50-MHz output frequency, with a two-tone IMD of -75 dBc at 71 MHz output.