Reliability of vertical MOSFETs for gigascale memory applications

被引：4
|
作者：
Goebel, B [1 ]
Bertagnolli, E [1 ]
Koch, F [1 ]
机构：
[1] Siemens AG, Corp Res & Dev, D-81730 Munich, Germany
来源：
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年
关键词：
D O I：
10.1109/IEDM.1998.746509
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We compare the reliability of vertical MOSFETs with planar ones. For the first time, the impact of the most striking vertical MOS specific features such as different source/drain engineering, channel orientation, and variable gate oxide thickness on reliability is investigated. Even though LDD is missing, it is shown that scaled down vertical transistors have a sufficient reliability for potential use in gigascale memories.
引用
收藏
页码：939 / 942
页数：4
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