An Adaptive Digital Background Calibration Technique Using Variable Step Size LMS for Pipelined ADC

被引：0

作者：

Abou-El-Kheir, Nahla T. ^{[1
]}

Abbas, Mohmed ^{[2
]}

Khedr, Mohamed Essam ^{[1
]}

机构：

[1] Arab Acad Sci & Technol, Elect & Commun Dept, Alexandria, Egypt

[2] Assiut Univ, Fac Engn, Dept Elect Engn, Assiut, Egypt

来源：

2014 9TH INTERNATIONAL SYMPOSIUM ON COMMUNICATION SYSTEMS, NETWORKS & DIGITAL SIGNAL PROCESSING (CSNDSP) | 2014年

关键词：

pipelined analog-to-digital converters; digital background calibration; variable step size; signed variable step size; modified variable step size;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper introduces an adaptive equalization based digital background technique suitable for correcting pipelined analog to digital converter (ADC) errors. Least mean square (LMS) technique with variable step size is used for adaptation. This technique is capable of fast tracking and calibration of different linear and nonlinear pipelined ADC errors. Different variable step size LMS prototypes are investigated and their performances are compared. The least number of iterations needed for convergence is found to be 5.8 KCycle. At input frequency of 9.99 MHz and sampling rate of 100 MSample/s, the calibration technique shows 42dB improvement in SFDR and 30dB in SNDR when deployed in a 12-bit pipelined ADC Simulink model. Furthermore, DNL of +0.25/-0.7 LSB and INL of +1.22/-2.3 are detected for the calibrated signal.

引用

页码：835 / 840

页数：6

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