Targeting Code Diversity with Run-time Adjustable Issue-slots in a Chip Multiprocessor

被引:0
|
作者
Anjam, Fakhar [1 ]
Nadecm, Muhammad [1 ]
Wong, Stephan [1 ]
机构
[1] Delft Univ Technol, Comp Engn Lab, Delft, Netherlands
来源
2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE) | 2011年
关键词
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中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents an adaptable softcore chip multiprocessor (CMP). The processor instruction set architecture (ISA) is based on the VEX ISA. The issue-width of the processor can be adjusted at run-time (before an application starts). The processor has eight 2-issue cores that can run independently from each other. If not in use, each core can be taken to a lower power mode by gating off its source clock. Multiple 2-issue cores can be combined at run-time to form a variety of configurations of very long instruction word (VLIW) processors. The CMP is implemented in the Xilinx Virtex-6 XC6VLX240T FPGA. It has a single ISA and requires no specialized compiler support. The CMP can target a variety of applications having instruction and/or data level parallelism. We found that applications/kernels with larger instruction level parallelism (ILP) performs better when run on a larger issue-width core, while applications with larger data level parallelism (DLP) performs better when run on multiple 2-issue cores with the data distributed among the cores.
引用
收藏
页码:1358 / 1363
页数:6
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