A novel automatic test pattern generator for asynchronous sequential digital circuits

被引：0
|
作者：
Dobai, Roland [1 ]
Gramatova, Elena [1 ]
机构：
[1] Slovak Acad Sci, Inst Informat, Bratislava 84507, Slovakia
来源：
MICROELECTRONICS JOURNAL | 2011年 / 42卷 / 03期
关键词：
Automatic test pattern generation; Asynchronous circuit; Hazard; Stuck-at fault; State justification; Sequential fault propagation; HAZARD DETECTION;
D O I：
10.1016/j.mejo.2010.10.013
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel automatic test pattern generator (ATPG) for stuck-at faults of asynchronous sequential digital circuits is presented. The developed ATPG does not require support by any design-for-testability method nor external software tool. The shortest test sequence generation is guaranteed by breadth-first search. The contribution is unique hazard identification before the test generation process, state justification on the gate level, sequential fault propagation based on breadth-first search and stepwise composition of state graphs for sequential test generation. A new six-valued logic together with a new algorithm was developed for hazardous transition identification. The internal combinational ATPG allows to generate test patterns one by one and only if it is required by sequential test generation. The developed and implemented ATPG was tested with speed-independent and quasi-delay-insensitive benchmark circuits. (C) 2010 Elsevier Ltd. All rights reserved.
引用
收藏
页码：501 / 508
页数：8
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