Design of a 8 Bit Current-Steering DAC for a GSM Transmitter

被引：0
|
作者：
Marin, Mihai-Eugen [1 ]
Brinzei, Catalin [2 ]
Constantinescu, Florin [1 ]
Gheorghe, Alexandru [1 ]
Ursac, Iulian [2 ]
机构：
[1] Univ Politehn Bucuresti, Dept Elect Engn, Bucharest, Romania
[2] Infineon Technol Romania SCS, Bucharest, Romania
来源：
2014 INTERNATIONAL SYMPOSIUM ON FUNDAMENTALS OF ELECTRICAL ENGINEERING (ISFEE) | 2014年
关键词：
Calibration; Current steering DAC; Digital to analog converter;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An 8 bit 1GSPs DAC targeting transmitters for mobile communications terminals has been implemented in 0.18 mu m TSMC technology. A correction scheme is used for the current sources in order to achieve a SFDR greater than 50dB after layout parasitic extraction in the 10MHz bandwidth. The simulated values for INL/DNL are 0.268 LSB and 0.377 LSB respectively. A 5+3 segmented architecture is used in order to reduce glitches. At 1Gbps sample rate, the total power consumption is estimated to be 15 mW on 2.5V/1.5V analog/digital supply voltages with a total die area of 0.23 mm(2).
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页数：5
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