Current and future challenges of DRAM metallization

被引：6

作者：

Weber, D ^{[1
]}

Thies, A ^{[1
]}

Kahler, U ^{[1
]}

Lepper, M ^{[1
]}

Schutz, R ^{[1
]}

机构：

[1] Infineon Technol, Memory Prod Div, D-01099 Dresden, Germany

来源：

PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2005年

关键词：

D O I：

10.1109/IITC.2005.1499974

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The challenges and requirements of current and future DRAM interconnect schemes are described. In contrast to most Logic metallization development and manufacturing, these requirements include tight pitches in array area, low resistance in the chip periphery, contacts with landing area smaller than the contacts themselves, AlCu fill into high aspect ratio contacts, continued drive toward lower capacitances and perhaps above all - low cost.

引用

页码：185 / 187

页数：3

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