A front-end electronics card comprising a high Gain/High bandwidth amplifier and a fast discriminator for time-of-flight measurements

During the development of the Multi-Strip Multi-Gap Resistive Plate Chambers (MMRPCs) for the Time-of-Flight (ToF) upgrade of the FOPI detector system, we have designed different versions of the Front-End Electronics (FEE). The signals from a MMRPC are read out on each side of the anode strips by an amplifier followed by a leading-edge discriminator. They are digitized in a Time-to-Amplitude Converter (TAC) followed by a Charge-to-Digital Converter (QDC). These counters are designed to provide a ToF resolution below sigma(t) <= 60 ps requiring an amplifier-discriminator stage with an intrinsic electronic resolution below sigma(t(FEE)) <= 20 ps. We describe the design steps of the FEE-card from a 4-channel version (FEE1) for the R&D phase to the final 16-channel card (FEE5) for the readout of 4800 channels of the total detector array. Through these design steps we have kept the following key characteristics: Low noise sigma(n) <= 25 mu V RMS (to the amplifier input), high gain (200) and a high bandwidth (1 GHz).