Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

被引：11

作者：

Lorenz, Juergen K. ^{[1
]}

Baer, Eberhard ^{[1
]}

Clees, Tanja ^{[2
]}

Jancke, Roland ^{[3
]}

Salzig, Christian P. J. ^{[4
]}

Selberherr, Siegfried ^{[5
]}

机构：

[1] Fraunhofer Inst Integrated Syst & Device Technol, D-91058 Erlangen, Germany

[2] Fraunhofer Inst Algorithms & Sci Comp SCAI, D-53754 St Augustin, Germany

[3] Fraunhofer Inst Integrated Circuits IIS EAS, Div Design Automat, D-01069 Dresden, Germany

[4] Fraunhofer Inst Ind Math ITWM, D-67663 Kaiserslautern, Germany

[5] Vienna Univ Technol, Inst Microelect, A-1040 Vienna, Austria

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2011年 / 58卷 / 08期

关键词：

Circuit simulation; manufacturability; process modeling; semiconductor device modeling; sensitivity; yield;

D O I：

10.1109/TED.2011.2150225

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. In this first of two consecutive papers, sources of process variations and the state of the art of related simulation tools are reviewed. An approach for hierarchical simulation of process variations including their correlations is presented. The second paper, also published in this issue, presents examples of simulation results obtained with this methodology.

引用

页码：2218 / 2226

页数：9

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