Layout-aware Analog Synthesis Environment with Yield Consideration

With shrinking device size in deep submicron process, many non-ideal effects impact circuit performances critically. Since those effects are often not considered in traditional analog synthesis tools, several sizing-layout iterations are still required to reach the desired performance and design yield. In this paper, an integrated analog synthesis tool is presented to consider the process variation, layout effects, and final layout generation simultaneously, with a user-friendly GUI to help users complete the design flow efficiently. With the consideration of those non-ideal effects in early design stages, blind design margins and time-consuming re-design cycles can be avoided in the proposed tool, which significantly reduces the design overhead. As shown in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds and effectively guarantees the post-layout performance and design yield with less hardware cost.