Steep slope 2D negative capacitance CMOS devices: MoS2 and WSe2

被引:0
|
作者
Si, Mengwei [1 ]
Ye, Peide D. [1 ]
机构
[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
来源
2018 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | 2018年
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暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This work reports steep slope sub-thermionic negative capacitance CMOS devices with 2D semiconductors as channel materials and ferroelectric hafnium zirconium oxide in the gate stack. Both n-type and p-type negative capacitance FETs are realized with MoS2 as n-type channel material and WSe2 as p-type channel material. Bidirectional sub-60 mV/dec at room temperature is achieved on both MoS2 and WSe2 negative capacitance FETs. The impact of internal metal gate on the performance of 2D negative capacitance FETs are also studied and compared with internal FETs.
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页数:2
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