Numerical and analytical simulations of Suspended Gate - FET for ultra-low power inverters

被引:4
|
作者
Tsamados, D. [1 ]
Chauhan, Y. S. [1 ]
Eggimann, C. [1 ]
Akarvardar, K. [2 ]
Wong, H. S. Philip [2 ]
Ionescu, Adrian M. [1 ]
机构
[1] Ecole Polytech Fed Lausanne, Lab Micro & Nanoelect Devices, CH-1015 Lausanne, Switzerland
[2] Stanford Univ, Stanford, CA 94305 USA
基金
美国国家科学基金会;
关键词
D O I
10.1109/ESSDERC.2007.4430905
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes, for the first time, the investigation of the SG-FET small slope switch based on a hybrid numerical simulation approach combining ANSYS (TM) Multiphysics and ISE-DESSIS (TM) in a self-consistent system. The proposed hybrid numerical simulations uniquely enables the investigation of the physics of complex Micro-Electro-Mechanical/solid-state devices, such as SG-FET. Abrupt switching and effect of gate charges are demonstrated. The numerical data serves to calibrate an analytical EKV-based SG-FET model, which is the used to design and originally simulate a sub-micron (90nm) scaled SG-FET complementary inverter. It is demonstrated that, due to abrupt switch in the subthreshold region and electro-mechanical hysteresis, the SG-FET inverter provides significant power saving (1-2 decades reduction of inverter peak current and practically, no leakage power) compared with traditional CMOS inverter.
引用
收藏
页码:167 / +
页数:2
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