Evaluation of Through-Silicon-Via Process using Scanning Laser Beam Induced Current (SLBIC) System

The manufacturing process of through-silicon-via (TSV) for 3D integration is complicated, and the high yield for each process is required. The relationship between the depth of the barrier/seed layer and the electroplating copper fill is investigated by using the scanning laser beam induced current (SLBIC) method. After reactive etching of via holes with diameters ranging from 50 mu m to 150 mu m, copper seed layer is deposited by sputtering, and then the electroplating of copper is performed. From the back surface of the sample, the infrared laser beam with wavelength of 1064nm was scanned, and the induced current between copper layer and silicon back surface is measured in order to obtain the current image. By changing the focus point of laser beam, the location of TSV failure is analyzed in depth direction.