RISC32-LP: Low-Power FPGA-Based IoT Sensor Nodes With Energy Reduction Program Analyzer

被引:9
|
作者
Tan, Beng-Liong [1 ]
Mok, Kai-Ming [1 ]
Chang, Jing-Jing [1 ]
Lee, Wai-Kong [2 ]
Hwang, Seong Oun [2 ]
机构
[1] Univ Tunku Abdul Rahman, Dept Comp & Commun Technol, Fac Informat & Commun Technol, Kampar 31900, Malaysia
[2] Gachon Univ, Dept Comp Engn, Seongnam 13120, South Korea
基金
新加坡国家研究基金会;
关键词
Internet of Things; Field programmable gate arrays; Energy consumption; Power demand; Hardware; Task analysis; Clocks; Clock gating (CG); dynamic voltage and frequency scaling (DVFS); energy saving; field-programmable gate array (FPGA); Internet of Things (IoT); low power; sensor nodes; ARCHITECTURE; VOLTAGE;
D O I
10.1109/JIOT.2021.3103035
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Field-programmable gate array (FPGA)-based sensor nodes are popular for their flexible design approach and field reconfigurability. RISC32 is one of the recent Internet of Things (IoT) processors proposed for the development of FPGA-based sensor nodes, and it includes the ability to reconfigure the microarchitecture on the fly in order to reduce dynamic energy consumption. However, such a method does not minimize static energy consumption, which is important in FPGA-based systems. In this work, clock gating (CG) and dynamic voltage and frequency scaling (DVFS) are applied to further reduce the energy consumption in RISC32. In the research presented here, we implemented a new software called the energy reduction program analyzer to estimate the parameters that configure a sensor node to achieve minimum energy consumption, targeting the typical IoT application scenario. Experimental results show that the low-power techniques applied in this work (RISC32-LP) can reduce energy consumption by 47%, compared to the standard RISC32 processor.
引用
收藏
页码:4214 / 4228
页数:15
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