Scalable gate-level models for power and timing analysis

被引：0

作者：

Badaroglu, Mustafa ^{[1
]}

Van der Plas, Geert ^{[2
]}

Wambacq, Piet ^{[2
,3
]}

Donnay, Stephane ^{[2
]}

Gielen, Georges ^{[4
]}

De Man, Hugo ^{[2
,4
]}

机构：

[1] AMI Semicond, Vilvoorde, Belgium

[2] MEC, Leuven, Belgium

[3] V U, Brussels, Belgium

[4] K U, Leuven, Belgium

来源：

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年

关键词：

D O I：

10.1109/ISCAS.2007.377865

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper we present a macromodeling methodology to accurately reproduce the timing and the peak/average power behaviors of digital standard cells for a wide range of operating conditions determined by the load, the input transition time, and the supply variations. Our methodology significantly reduces the number of transient simulations for the cell characterization. The numerical results for the transient simulation of large digital systems indicate that we achieve a mean error of 10% for the power consumption and 4% for the propagation delay of the complete digital system while the mean error for the used gates in this system is 2.5% when compared to SPICE-based simulations.

引用

页码：2938 / +

页数：2

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