共 50 条
- [21] MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank 2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2021, : 601 - 606
- [25] Work-in-Progress: Efficient Low-latency Near-Memory Addition 2022 INTERNATIONAL CONFERENCE ON COMPILERS, ARCHITECTURE, AND SYNTHESIS FOR EMBEDDED SYSTEMS (CASES 2022), 2022, : 33 - 34
- [26] BAT: Boundary aware transducer for memory-efficient and low-latency ASR INTERSPEECH 2023, 2023, : 4963 - 4967
- [28] A Memory-Efficient Architecture for Low Latency Viterbi Decoders 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2009, : 335 - 338
- [30] Low-Latency LDPC Decoding Achieved by Code and Architecture Co-Design PROCEEDINGS OF 2018 IEEE 10TH INTERNATIONAL SYMPOSIUM ON TURBO CODES & ITERATIVE INFORMATION PROCESSING (ISTC), 2018,