Design of power electronic digital controller based on FPGA/SOC using VHDL-AMS language

被引：6

作者：

Jovanovic, Slavisa ^{[1
]}

Poure, Philippe ^{[1
]}

机构：

[1] Univ Nancy 1, LIEN, EA 3440, F-54506 Vandoeuvre Les Nancy, France

来源：

2007 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, PROCEEDINGS, VOLS 1-8 | 2007年

关键词：

D O I：

10.1109/ISIE.2007.4374966

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, authors detail a Top-down design methodology for Power Electronic digital controller based on Field Programmable Gate Aray or System-On-Chip. This design now uses VHDL-AMS language. The application case of a shunt three phase power active filter is studied. An optimised architecture is designed and each step is detailed. Each block of the architecture is modeled in VHDL at several abstraction levels, from real data format to specific binary format. To achieve closed loop simulation, analog and power elements are modeled in VHDL-AMS. The whole closed loop system is successfully validated at various abstraction levels of the,digital control, using ADVanceMS.

引用

页码：2301 / 2306

页数：6

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