An improvement of SOA on n-channel SOI LDMOS transistors

被引：6

作者：

Yang, IS ^{[1
]}

Koh, YH ^{[1
]}

Jeong, JH ^{[1
]}

Choi, YS ^{[1
]}

Kwon, OK ^{[1
]}

机构：

[1] Hanyang Univ, Dept Elect Engn, Seongdong Gu, Seoul 133791, South Korea

来源：

ISPSD '98 - PROCEEDINGS OF THE 10TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS | 1998年

关键词：

D O I：

10.1109/ISPSD.1998.702722

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new n-channel SOI LDMOS transistor which has the n(+) drain structure with a buffer layer is proposed. The electric field of n(+) drain region can be reduced by 68 percent in this structure compared with conventional LDMOSFETs. The generation of hole current, which turns on a parasitic bipolar transistor and causes the second breakdown, can be suppressed. This device was fabricated in the 0.8 mu m CMOS process on a SOI wafer and the doping concentration of a buffer layer was optimized by simulations. From the measurement results, it was confirmed that the second breakdown voltage at V-gs=20V was improved from 35V to 80V in the proposed structure. And this device has the breakdown voltage of 240V and the specific on resistance of 16.9 m Omega . cm(2) which is the best reported performance for this voltage range.

引用

页码：379 / 382

页数：4

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