An improvement of SOA on n-channel SOI LDMOS transistors

A new n-channel SOI LDMOS transistor which has the n(+) drain structure with a buffer layer is proposed. The electric field of n(+) drain region can be reduced by 68 percent in this structure compared with conventional LDMOSFETs. The generation of hole current, which turns on a parasitic bipolar transistor and causes the second breakdown, can be suppressed. This device was fabricated in the 0.8 mu m CMOS process on a SOI wafer and the doping concentration of a buffer layer was optimized by simulations. From the measurement results, it was confirmed that the second breakdown voltage at V-gs=20V was improved from 35V to 80V in the proposed structure. And this device has the breakdown voltage of 240V and the specific on resistance of 16.9 m Omega . cm(2) which is the best reported performance for this voltage range.