On-Chip Checkpointing with 3D-Stacked Memories

Since deep-submicron process technologies induce soft errors, advanced computing systems face a low dependability problem. Checkpointing, which copies data required for continuing the program execution as a backup, is expected as a promising approach to keeping a high dependability. However, checkpointing causes additional memory accesses, which cause performance and energy overheads. To reduce these overheads, this paper focuses on 3D-stacking technologies. Since the technologies realize large on-chip memories with a short latency and a high bandwidth, the overheads of checkpointing are expected to decrease. In order to examine the reduction of the overheads, this paper supposes a future 3D-stacked processor-memory module, and proposes an on-chip checkpointing mechanism. The evaluation results indicate that the on-chip checkpointing with 3D-stacked memories can reduce the execution time by 15% and energy consumption by 26% on average, compared with the checkpointing mechanism with off-chip memories.