An 84 dB Dynamic Range 62.5-625 kHz Bandwidth Clock-Scalable Noise-Shaping SAR ADC with Open-Loop Integrator using Dynamic Amplifier

This paper proposes a noise shaping SAR ADC with open-loop integrator using dynamic amplifier. The proposed integrator for a delta-sigma modulator requires low-gain open loop amplifiers, therefore low power dynamic amplifier can be used. Moreover, binary-mode dynamic element matching is proposed to overcome the nonlinearity of a capacitor DAC. An SNDR of 83.5 dB, a power consumption 273.4 mu W, and a Schreier figure of merit of 173 dB with a bandwidth of 250 kHz is achieved. In addition, clock scalability has been confirmed for a wide sampling-rate range of 2.5 MS/s to 25 MS/s.