Low power dual-port CMOS SRAM macro design

被引：0
|
作者：
Wang, H
Liu, PC
Lau, KT
机构：
[1] Microelectronics Center, Sch. of Elec. and Electron. Eng., Nanyang Technological University
来源：
ELECTRONICS LETTERS | 1996年 / 32卷 / 15期
关键词：
integrated memory circuits; CMOS integrated circuits;
D O I：
10.1049/el:19960907
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel low power dual-port CMOS SRAM structure is described. The inherent low power advantage is obtained by using current-mode rather than voltage-mode signal transmission. The design of this new dual-port memory cell and current-mode sense amplifier is based on 0.5 mu m, 5V CMOS logic process technology. HSPICE simulations show that the circuits can operate at high speed even if the supply voltage is reduced to 2V. The dual-port memory cell is most suitable for the design of FIFO buffers.
引用
收藏
页码：1354 / 1356
页数：3
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