DAMQ self-compacting buffer schemes for systems with network-on-chip

被引：0
|
作者：
Liu, J [1 ]
Delgado-Frias, JG [1 ]
机构：
[1] Washington State Univ, Sch Elect Engn & Comp Sci, Pullman, WA 99164 USA
来源：
CDES '05: PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN | 2005年
关键词：
network on chip; systems-on-chip; DAMQ buffer; interconnection network;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we present two novel buffer schemes for systems-on-chip applications that have an interconnection network. The proposed schemes are based on a DAMQ self-compacting buffer. These schemes outperform existing approaches. In addition the schemes have similar performance using only half of the buffer size used in other implementations. One of our schemes (DAMQ(min)) provides an excellent technique to optimize buffer management providing a good throughput when the network has large load.
引用
收藏
页码：97 / 103
页数：7
相关论文
共 50 条
  • [31] Xpipes: A network-on-chip architecture for gigascale systems-on-chip
    Bertozzi, Davide
    Benini, Luca
    IEEE Circuits and Systems Magazine, 2004, 4 (02) : 18 - 31
  • [32] Runtime buffer management to improve the performance in irregular Network-on-Chip architecture
    Umamaheswari, S.
    Meganathan, D.
    Perinbam, Raja Paul J.
    SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES, 2015, 40 (04): : 1117 - 1137
  • [33] Runtime buffer management to improve the performance in irregular Network-on-Chip architecture
    S U.
    D M.
    Perinbam J R.P.
    Sadhana, 2015, 40 (4) : 1117 - 1137
  • [34] A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture
    Wang, Jian
    Li, Yubai
    Li, Huan
    ADVANCES IN ELECTRICAL AND COMPUTER ENGINEERING, 2012, 12 (04) : 19 - 24
  • [35] Optimized buffer protection for network-on-chip based on Error Correction Code
    Pinheiro, Alan
    Tavares, Daniel
    Silva, Felipe
    Silveira, Jarbas
    Marcon, Cesar
    MICROELECTRONICS JOURNAL, 2020, 100 (100):
  • [36] Optimized Fault-Tolerant Buffer Design for Network-on-Chip Applications
    Pinheiro, Alan C.
    Silveira, Jarbas A. N.
    Tavares, Daniel A. B.
    Silva, Felipe G. A.
    Marcon, Cesar A. M.
    2019 IEEE 10TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2019, : 217 - 220
  • [37] UBERNoC: Unified Buffer Power-Efficient Router for Network-on-Chip
    Farrokhbakht, Hossein
    Kao, Henry
    Jerger, Natalie Enright
    PROCEEDINGS OF THE 13TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS'19), 2019,
  • [38] The influence of cementitious systems to cracking sensitivity of self-compacting concrete
    Wang, Guojie
    Zheng, Jianlan
    1st International Symposium on Design, Performance and Use of Self-Consolidating Concrete, 2005, 42 : 457 - 464
  • [39] A Novel Optical Mesh Network-on-Chip for Gigascale Systems-on-Chip
    Gu, Huaxi
    Xu, Jiang
    Wang, Zheng
    2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 1728 - +
  • [40] Scalable THz Network-On-Chip Architecture for Multichip Systems
    Tahanian, Esmaeel
    Tajary, Alireza
    Rezvani, Mohsen
    Fateh, Mansoor
    JOURNAL OF COMPUTER NETWORKS AND COMMUNICATIONS, 2020, 2020 (2020)
12345