Global interconnect optimization and impact of inductance on the overall performance

With aggressive scaling of CMOS technology, different performance parameters: latency, bandwidth, repeater power consumption and area, and delay variation of global interconnects are not scaling accordingly with those of devices and local interconnects. There have been various optimization schemes to minimize the discrepancy of performance between the devices and global interconnect lines. Typically the thickness of metal lines and dielectric layers for a given process technology can not be changed by the circuit designers; and many figures of merit (FOMs) as functions of interconnect width and/or spacing are proposed to optimize bandwidth and delay. But these optimization schemes are based on RC delay concepts, which assume that the total inductance is less than a critical inductance and the system is over damped; hence the impact of inductance can be ignored. This paper will attempt to identify the limitations of these figures of merit (FOMs), and address the impact of line inductance on the methodology of global interconnect width and spacing optimization, and on different figures of merit (FOMs). The paper will examine the impacts of inductance on various performance parameters, such as, band width, delay, delay uncertainty, and repeater power and area, which were previously based on RC models.