As traditional poly-silicon gated MOSFET devices scale, the additional series capacitance due to poly-silicon depletion becomes an increasingly large fraction of the total gate capacitance, excessive boron penetration causes threshold voltage shifts, and the gate resistance is elevated. To solve these problems and continue aggressive device scaling we are studying metal electrodes with suitable work-functions and sufficient physical and electrical stability. Our studies of metal gates on HfO2 indicate that excessive inter-diffusion, inadequate phase stability, and interfacial reactions are mechanisms of failure at source drain activation temperatures that must be considered during the electrode selection process. Understanding the physical properties of the metal gate - HfO2 interface is critical to understanding the electrical behavior of MOS devices. Of particular interest is Fermi level pinning, a phenomenon that occurs at metal dielectric interfaces which causes undesirable shifts in the effective metal work function. The magnitude of Fermi level pinning on HfO2 electrodes is studied with Pt and LaB6 electrodes. In addition, the intrinsic and extrinsic contributions to Fermi level pinning of platinum electrodes on HfO2 gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the work function of platinum-HfO2-silicon capacitors. The presence of interfacial oxygen vacancies or Pt-Hf bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the MIGS model alone. Interface chemistry and defects influence the effective metal work function.
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Osaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan
Ando, Takashi
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Shimura, Takayoshi
Watanabe, Heiji
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Osaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan
Watanabe, Heiji
Hirano, Tomoyuki
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Sony Corp, Semicond Business Grp, Semicond Technol Dev Div, Kanagawa 2430014, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan
Hirano, Tomoyuki
Yoshida, Shinichi
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Sony Corp, Semicond Business Grp, Semicond Technol Dev Div, Kanagawa 2430014, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan
Yoshida, Shinichi
Tai, Kaori
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Sony Corp, Semicond Business Grp, Semicond Technol Dev Div, Kanagawa 2430014, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan
Tai, Kaori
Yamaguchi, Shinpei
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Sony Corp, Semicond Business Grp, Semicond Technol Dev Div, Kanagawa 2430014, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan
Yamaguchi, Shinpei
Iwamoto, Hayato
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Sony Corp, Semicond Business Grp, Semicond Technol Dev Div, Kanagawa 2430014, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan
Iwamoto, Hayato
Kadomura, Shingo
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Sony Corp, Semicond Business Grp, Semicond Technol Dev Div, Kanagawa 2430014, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan
Kadomura, Shingo
Toyoda, Satoshi
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Univ Tokyo, Grad Sch Engn, Dept Appl Chem, Bunkyo Ku, Tokyo 1138656, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan
Toyoda, Satoshi
Kumigashira, Hiroshi
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Univ Tokyo, Grad Sch Engn, Dept Appl Chem, Bunkyo Ku, Tokyo 1138656, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan
Kumigashira, Hiroshi
Oshima, Masaharu
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Univ Tokyo, Grad Sch Engn, Dept Appl Chem, Bunkyo Ku, Tokyo 1138656, JapanOsaka Univ, Grad Sch Engn, Dept Mat & Life Sci, Suita, Osaka 5650871, Japan