A Comprehensive Performance Evaluation to GPGPU Applications under STT-RAM based Hybrid Cache Architectures

Nowadays, general purpose Graphic Processing Units (GPGPUs) have become the technical trend for complex science and engineering computing in the exascale, which is through its unique capability of massive parallel computing based on the many-core architecture. Also, the occurrence probability of soft errors caused by particle strike on the large-scale computing system built by GPGPUs has been boosted significantly. Spin-Transfer Torque RAM (STT-RAM) benefits from its unique way of carrying information through a Magnetic Tunnel Junction (MTJ), and then it is a feasible soft error resilient solution due to its immunity to soft errors. However, STT-RAM suffers from the large overhead of latency and energy consumption on write operations, and thus results in hesitating of adopting STT-RAM into memory system design. Therefore, it is very necessary to do a comprehensive performance evaluation of adopting the STT-RAM into the memory hierarchy of the GPGPU architecture (i.e., hybrid STT-RAM/SRAM cache architectures). This work offers a fair and comprehensive performance evaluation for GPGPU applications based on different cache associativities and multiple plans of partial or complete adopting STT-RAM into the memory hierarchy of the GPGPU, which could offer useful options for the soft error resilient GPGPU architecture design. In addition, this work encloses that a proper combination of cache configuration and adoption plan may result in only slight timing performance drop and equivalent energy consumption performance, while taking advantage of the soft error resilience.