Research on VHDL RTL synthesis system

In this paper, we present a prototype of VHDL RTL synthesis system- VHB. This prototype can be divided into three parts. The first part is a VHDL synthesis subset parser, the second part is an optimizer at language level, and the third part is an inferencer responsible for getting the netlist. The parser checks whether the input VHDL descriptions are in accordance with the grammar of synthesis subset, and generates the parsing tree of input descriptions. The parsing tree generated by the parser is provided to the second part of the prototype to perform language level optimization, which includes redundant and ambiguous elimination in assignment statements; expression optimization; common sub-expression extraction; operator reordering; resource sharing and loop unrolling. The task of the third part is very simple, which generates the netlist.