Investigation of Stepwise Charging Circuits for Power-Clock Generation in Adiabatic Logic

被引：0

作者：

Raghav, Himadri Singh ^{[1
]}

Bartlett, Vivian A. ^{[1
]}

Kale, Izzet ^{[1
]}

机构：

[1] Univ Westminster, Appl DSP & VLSI Res Grp, Dept Engn, London W1W 6UW, England

来源：

2016 12TH CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME) | 2016年

关键词：

power-clocks; adiabatic circuits; stepwise charging; tank-capacitor; energy recovery;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery properties and complexity. We show that energy recovery achievable depends on the tank-capacitor size. We also show that tank-capacitor sizes can be reduced as their number increases concluding that combined tank capacitance (CTT) versus load capacitance (CL) ratio is the significant parameter. We propose that using a CTT/CL ratio of 10 and using a 4-step charging power-clock constitute appropriate trade-offs in practical circuits.

引用

页数：4

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