A Low-Offset Dynamic Comparator with Area-Efficient and Low-Power Offset Cancellation

A low-offset two-stage dynamic comparator has been proposed for parallel multi-channel processing. Low offset is achieved from two aspects: 1st-stage offset cancellation and 2nd-stage offset suppression. A fully dynamic offset cancellation scheme based on current auto-zeroing is adopted to effectively cancel out the 1st-stage offset. It features small area overhead and low energy consumption. For the 2nd-stage offset suppression, a high gain is designed for the 1st-stage dynamic amplifier by optimizing the overdrive voltage of input transistors. To maintain low offset performance across a wide range of input common-mode voltages, the overdrive voltage of the input pair is required to stay low. Therefore, a tail current source is employed for the 1st stage to ensure constant common-mode discharging current. As a result, the overdrive voltage can be stably kept low under various operation conditions. The proposed comparator has been designed in a standard CMOS 0.18 mu m process. It operates under a supply voltage of 1.2 V at 10 MHz. Simulation results have verified the low-offset property of the comparator. The inputreferred offset (1 sigma) is reduced from 19.25 mV to 1.296 mV after cancellation and it remains constant with the input common-mode voltage changing from 0 V to 0.8 V. The offset is further reduced to 771 mu V when the 2nd-stage input pair are enlarged by 4 times. At the same time, the energy consumption is increased from 147 fJ/Conv to 168 fJ/Conv.