Failure analysis of metal bridging & yield enhancement of wafer fabrication

被引：0

作者：

Hua, YN ^{[1
]}

Chu, TP ^{[1
]}

Guo, ZR ^{[1
]}

An, LH ^{[1
]}

Chong, KK ^{[1
]}

Koh, CF ^{[1
]}

机构：

[1] Chartered Semicond Mfg Ltd, Singapore 118222, Singapore

来源：

ISIC-99: 8TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, DEVICES & SYSTEMS, PROCEEDINGS | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, failure analysis was performed on some low yield wafers (0.8 un device). Optical & SEM inspection did not find any visual defects or contamination at first. However, after depassivation using RIE, surface SEM I inspection on metal 2 layer found an interesting result that metal 2 filaments were found at a particular dense metal 2 area with the minimum spacing design rule. EDX analysis confirmed that they were Al & barrier metal (TiW) filaments that had caused metal bridging failure and resulted in low yield issue. The metal filaments mere due to poor planarization of IMD layers. In this paper, details of failure analysis results will be reported. General solution to eliminate the metal filament is to increase etching time during metal etching. However, it will result in some side effect such as metal thinning issue. Therefore, in this study, a solution improving IMD planarization by decreasing BPSG oxide loss & using high dispense volume SOG will be introduced. After taking some corrective actions and using a set of new fab processes, the metal filaments were eliminated & the yield has been greatly enhanced.

引用

页码：87 / 89

页数：3

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