Design techniques for high speed serial data transmitters in CMOS process

被引：0

作者：

Yoo, CS ^{[1
]}

Lee, IG ^{[1
]}

Yoon, KH ^{[1
]}

Kim, WC ^{[1
]}

Chai, SH ^{[1
]}

Song, WC ^{[1
]}

机构：

[1] ELECTR & TELECOMMUN RES INST,HIGH SPEED CIRCUITS SECT,TAEJON 305350,SOUTH KOREA

来源：

ELECTRICAL ENGINEERING | 1996年 / 79卷 / 02期

关键词：

D O I：

10.1007/BF01232920

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An STM-4 rate serial data transmitter (SDT) is implemented using a 0.8 mu m CMOS process. The charge injection method is adopted for the delay cells in the VCO to enhance the oscillation frequency. By optimizing the combination of NOR gates in the shift register, the delay of the data serializer is reduced. Probable timing errors are avoided by phase reversal of the serial data clock. It dissipates about 700 mW at 624 Mbps.

引用

页码：113 / 117

页数：5

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