A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

被引：6
|
作者：
Lin, Li [1 ]
Ren, Junyan [1 ]
Zhu, Kai [1 ]
Ye, Fan [1 ]
机构：
[1] Fudan Univ, State Key Lab ASIC & Syst, Micro Nano Elect Innovat Platform, Shanghai 201203, Peoples R China
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2009年 / 58卷 / 01期
关键词：
Analog-to-digital converter; CMOS analog integrated circuits; Folding; Interpolating;
D O I：
10.1007/s10470-008-9222-5
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 1-GS/s 6-bit two-channel time-interleaved folding and interpolating analog-to-digital converter (ADC) is presented in this article. For low voltage applications, input-connection-improved active interpolating amplifiers and cascaded folding amplifiers have been applied. A single front-end track-and-hold (T/H) circuit is used to avoid the sampling-time mismatches between the channels. When supplied with 1.4 V, the circuit achieves signal-to-noise-plus-distortion ratio (SNDR) of 30.74 dB and spurious free dynamic range (SFDR) of 36.91 dB and consumes a power of 66 mW with 500-MHz input and 1-GS/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.57 and 0.81 LSB, respectively. The figure of merit (FoM) is 1.75 pJ/conversionstep. The ADC circuit is prototyped in 0.13-mu m CMOS process and occupies a core area of 0.45 mm(2).
引用
收藏
页码：71 / 76
页数：6
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