A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization

被引：0

作者：

Gal-Katziri, Matan ^{[1
]}

Hajimiri, Ali ^{[1
]}

机构：

[1] CALTECH, Dept Elect Engn, Pasadena, CA 91125 USA

来源：

2018 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC): PROCEEDINGS OF TECHNICAL PAPERS | 2018年

关键词：

CMOS integrated circuits; phased-arrays; radio frequency; tracking loops; delay-lines; phase locked loops; phase noise; RECEIVER; QUAD;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A large-scale timing synchronization scheme for scalable phased arrays is presented. This approach utilizes a DLL co-designed with a subsequent 2.5GHz PLL. The DLL employs a low noise, fine/coarse delay tuning to reduce the in-band rms jitter to 323fs, an order of magnitude improvement over previous works at similar frequencies. The DLL was fabricated in a 65nm bulk CMOS process and was characterized from 27MHz to 270MHz. It consumes up to 3.3mW from a 1V power supply and has a small footprint of 0.036mm(2).

引用

页码：231 / 234

页数：4

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