High-Yield Design of High-Density SRAM for Low-Voltage and Low-Leakage Operations

The minimum functional voltage of System-On Chip manufactured in recent technology nodes is often that of its Static Random-Access Memories (SRAM). Operating SRAM at subnominal voltage requires the use of additional circuits named assist circuits. This paper details the write assist and the temperature- and process-compensated read assist circuits used against insufficient bitcell Write Margin (WM) and Static Noise Margin (SNM), respectively. A new graphic tool named yieldogram is introduced to monitor clearly over a supported temperature range the capacity-dependent safe design region at various yield targets, including the highest industrial standard (1ppm), and is used to evaluate graphically the effects of different combinations of assist. We show that our implementation of WordLine UnderDrive (WLUD) assist technique against SNM limitations has a minimum impact on the performance, since it is temperature- and process-compensated, while negative BitLine implementation against WM limitations improves performances. The combined use of both techniques allows to gain more than 20% Vddmin, improving the frequency by 15%, decreasing dynamic power by 10% with worst-case increases in area and static power of 10 %. Finally, with a small WLUD overhead, yield can be obtained on Mass-Scale Production even after ageing.