Design of an ASIC chip for skeletonization of graylevel digital images

被引：1

作者：

Majumdar, B ^{[1
]}

Ramakrishna, VV ^{[1
]}

Dey, PS ^{[1
]}

Majumdar, AK ^{[1
]}

机构：

[1] INDIAN INST TECHNOL,DEPT COMP SCI & ENGN,KHARAGPUR 721302,W BENGAL,INDIA

来源：

VLSI DESIGN | 1996年 / 4卷 / 01期

关键词：

ASIC; VLSI design; image processing; skeletonization; image thinning;

D O I：

10.1155/1996/51972

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the design of an ASIC chip for thinning of graylevel images. The chip implements a Min-Mau skeletonization algorithm and is based on a pipeline architecture where each stage of the pipeline performs masking operations on the graylevel images. The chip operates in real time at a frequency of 8 MHz and utilizes about 321 mils X 410 mils of silicon area.

引用

页码：83 / 90

页数：8

共 50 条

[31] A study on an ASIC design technique for digital protective relays
Seo, J
Shin, MC
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 3910 - 3913
[32] Testable design of digital ASIC with embedded analog multiplexers
Jankovic, S
Maksimovic, D
Petkovic, P
Litovski, V
1997 21ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, VOLS 1 AND 2, 1997, : 779 - 782
[33] Long Term On-Chip Monitoring of SET Pulsewidths in a Fully Digital ASIC
Veeravalli, Varadan Savulimedu
Steininger, Andreas
PROCEEDINGS OF THE 22ND AUSTRIAN WORKSHOP ON MICROELECTRONICS (AUSTROCHIP 2014), 2014, : 41 - 46
[34] Design and Implementation of Skeletonization
Gunadi, Kartika
Liliana
Simon, Gideon
INTELLIGENCE IN THE ERA OF BIG DATA, ICSIIT 2015, 2015, 516 : 314 - 322
[35] Architecture for hardware thinning and crest restoration in graylevel images
Akil, M
REAL-TIME IMAGING VIII, 2004, 5297 : 242 - 253
[36] Design of a QPSK demodulator for DVB-S receiver ASIC chip
Yang, H
Lin, Z
Cai, XF
2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 2075 - 2078
[37] Detecting Hardware Trojans using On-chip Sensors in an ASIC Design
Kelly, Shane
Zhang, Xuehui
Tehranipoor, Mohammed
Ferraiuolo, Andrew
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2015, 31 (01): : 11 - 26
[38] Design of MEMS gyroscope interface ASIC with on-chip temperature compensation
Zhang, Huan
Chen, Weiping
Yin, Liang
Fu, Qiang
MEASUREMENT, 2023, 220
[39] Design of a QPSK/16 QAM LMDS downstream receiver ASIC chip
Park, KH
Shin, DK
Lee, JS
Sunwoo, MH
2000 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION, 2000, : 210 - 217
[40] EDA/ASIC vendors cooperate on standards for system-on-a-chip design
Tuck, B
COMPUTER DESIGN, 1998, 37 (08): : 20 - +

← 1 2 3 4 5 →