Design of an ASIC chip for skeletonization of graylevel digital images

被引：1

作者：

Majumdar, B ^{[1
]}

Ramakrishna, VV ^{[1
]}

Dey, PS ^{[1
]}

Majumdar, AK ^{[1
]}

机构：

[1] INDIAN INST TECHNOL,DEPT COMP SCI & ENGN,KHARAGPUR 721302,W BENGAL,INDIA

来源：

VLSI DESIGN | 1996年 / 4卷 / 01期

关键词：

ASIC; VLSI design; image processing; skeletonization; image thinning;

D O I：

10.1155/1996/51972

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the design of an ASIC chip for thinning of graylevel images. The chip implements a Min-Mau skeletonization algorithm and is based on a pipeline architecture where each stage of the pipeline performs masking operations on the graylevel images. The chip operates in real time at a frequency of 8 MHz and utilizes about 321 mils X 410 mils of silicon area.

引用

页码：83 / 90

页数：8

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