SiC Trench MOSFET With Reduced Switching Loss and Increased Short-Circuit Capability

In this article, a novel SiC trench MOSFET with deep p(+) shielded regions and current spreading layers (CSLs) (DPCSL-MOS) is proposedand studied by TCAD simulations. The results show that the introduction of the deep p+ shielded region reduces the transfer capacitance C-rss (= C-gd) and the saturation current, thus reducing the total switching losses and increasing the short-circuit capability. Besides, the deep p+ regions around the source trench efficiently shields the shallow gate trench from the drain voltage, thus reducing the maximum oxide electric field. In addition, the introduction of CSL with higher doping concentration than the drift layer brings down the JFET effect and the resultant device ON-resistance. The dynamic figure of merit (FOM) (R-ON * Q(gd)) is significantly improved with no degradation in terms of the static FOM (V-br(2)/R-ON). Therefore, the proposed DPCSL-MOS is a more robust and promising structure for power electronic systems, especially for the high-frequency applications.