Chip level three-dimensional assembling of microsystems

被引:4
|
作者
Toshiyoshi, H [1 ]
Mita, Y [1 ]
Ogawa, M [1 ]
Fujita, H [1 ]
机构
[1] Univ Tokyo, Inst Ind Sci, Minato Ku, Tokyo 1068558, Japan
关键词
ICP-RIE; three-dimensional assemble; assembling; connector; receptacle; motherboard;
D O I
10.1117/12.341260
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
We propose a new method of assembling three-dimensional microsystems by means of chip level electrical interconnection. Silicon dies are flip-chipped out of a silicon wafer by using ICP-RLE (inductively coupled plasma - reactive ion etching) instead of a dicing saw. Fringes of the chips are patterned into pin-shapes so that they can be vertically inserted into the micro motherboard for electrical and physical connection. The pins are coated with Cr-Au, and the contact pads are electroplated with Cu for low contact resistance (0.18 Ohm/contact). The pins are tapered in width, and assembling was easily done by manual positioning under the optical binocular microscope. This technique is a break through to the hybrid integration of various kind of micro chips independent of material or fabrication compatibility.
引用
收藏
页码:679 / 686
页数:8
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